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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. february 2007 rev 1 1/37 1 SPEAR-09-H122 spear? head600 features arm926ej-s core @333mhz. 600kbyte reconfigurable logic array with 88 dedicated general purposes i/os, 9 lvds channels and 128kbyte configurable internal memory pool. multilayer amba 2.0 compliant bus with f max 166mhz 32kbyte rom. 8kbyte common static ram. dynamic power saving features. high performance 8 channels dma. ethernet 10/100/1000 mac with gmii/mii interface to external phy. usb2.0 device with integrated phy. 2 usb2.0 host with integrated phy. ext. sdram memory interface: ? 8/16bit (ddr1@200mhz) ? 8/16bit (ddr2@333mhz) flashes interface: ? nand 8/16bit ? serial (up to 50mbps). 3-spi master/slave up to 40mbps. i 2 c master/slave mode - high, fast and slow speed. 2 independent uart up to 460.8 kbps with software flow control mode. irda (fir-mir-sir) from 9.6kbps to 4mbps speed-rate. colour lcd controller: ? up to 1024x768 resolutions. ? 24bpp true colour tft panel. ? 16bpp dstn panel. 10 gpios bidirectional signals with interrupt capability. 88 ras-gpios user customizable bidirectional signals (up to 4 clocks). adc 10 bit, 1msps, 8 analog inputs. jpeg codec accelerator. 10 independent timers with programmable prescaler. real time clock. watchdog system controller misc internal control registers. jtag (ieee1149. 1) interface description spear head600 is a powerful digital engine belonging to spear family, the innovative customizable system on chip. the device integrates an arm 926 core with a large set of proven ips and a big configurable logic block that allow very fast customization of unique and/or proprietary solution. pbga420 table 1. device summary part number op. temp. range, c package packing SPEAR-09-H122 -40 to 85 pbga420(23x23x1.81mm) tray www.st.com
contents SPEAR-09-H122 2/37 contents reference documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 architecture properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 functional pin group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 special ios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.1 usb 2.0 transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.2 sstl_2/sstl_18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.3 lvds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 main memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 icm1 - low speed connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 icm2 - application subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 icm4 - high speed connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5 ml1, 2 - multi layer cpu subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.6 icm3 - basic subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 7.1 cpu subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.2 cpu arm 926ej-s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.1 crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.2 crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4.1 rtc crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4.2 rtc crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SPEAR-09-H122 contents 3/37 4.5 ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6 usb2 host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.7 usb2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.8 low jitter pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.9 reconfigurable logic array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9.2 custom project development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9.3 customization process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9.4 adc controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.10 other interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.10.1 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.10.2 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
list of tables SPEAR-09-H122 4/37 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description by functional group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4. main memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5. icm1 - low speed connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. icm2 - application subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. icm4 - high speed connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. ml1, 2 - multi layer cpu subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. icm3 - basic subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. main oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. rtc oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SPEAR-09-H122 list of figures 5/37 list of figures figure 1. main spear head600 func tional interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4. crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 5. rtc crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 6. rtc crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7. pbga420 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
reference documentation SPEAR-09-H122 6/37 reference documentation 1. arm926ej-s - technical reference manual 2. amba 2.0 specification 3. eia/jesd8-9 specification 4. usb2.0 specification 5. ohci specification 6. ehci specification 7. usb specification 8. ieee 802.3 specification 9. i 2 c - bus specification
SPEAR-09-H122 product overview 7/37 1 product overview an outline picture of the main spear head600 functi onal interfaces is shown in figure 1 . figure 1. main spear head600 functional interfaces 1.1 features the following main functionalities are implemented in the spear head600 soc device: arm926ej-s core @333mhz, 16kb-i/d cache, configurable tmc-i/d size, mmu, tlb, jtag and etm trace module (multiplexed interfaces). 600kbyte reconfigurable logic array (programmable through 4metal and 4vias). 128kbyte configurable internal memory pool (single and dual port memory). 32kbyte rom (code customizable) 8kbyte common sram. dynamic power save features. high performance linked list 8 channels dma. ethernet gmii/mii (ieee802.3/3x/1q), management i/f. usb2.0 device (high-full-slow speed); integrated phy transceiver. 2-usb2.0 host (high-full-slow sp eed); integrated phy transceiver. ext. memory i/f: 8/16bit ddr1@200mhz/ddr2@333mhz. flash interface: nand 8/16bit and serial (up to 50mbps). 3-spi master/slave (motorola-texas-national) up to 40mbps. i 2 c (high-fast-slow speed) master/slave. 2-uart (speed rate up to 460.8kbps). irda (fir-mir-sir) from 9.6kbps to 4mbps speed-rate. color lcd up to 1024x768 resolutions; 24bpp true colour; stn/tft display panel. 10 gpios bidirectional sign als with interrupt capability. 9 lvds (8 out and 1 input) signals; customizable interface through programmable logic. 88 ras-gpios user customizable bidirectional signals (up to 4 clocks). spear head600 gmii/mii usb2.0 dev usb2.0 host(2) clcd ddr 1/2 pl_gpios pl_lvdss jtag & test i2c spis (3) uarts (2) irda gpios adcs flash serial flash nand
product overview SPEAR-09-H122 8/37 adc (1us/1msps) 8 analog input channel; 10bit approximation. jpeg codec accelerator 1clock/pixel. 10 independent timers with programmable prescaler. rtc - wdog - sysctr - misc internal control registers. jtag (ieee1149.1) interface. 1.2 architecture properties power save features: ? operating frequency sw programmable. ? clock gating functionality. ? low frequency operating mode. ? automatic power saving controlled from application activity demands. customizable logic to embed the customer real 'core competence': ? 600kgate standard cell array. ? internal memory pool (128 kbyte) full configurable. ? up to 16 external/internal source clock (some of these programmable). ? three memory path toward the sdram controller to ensure a good bandwidth. architecture easily extensible. external memory bandwidth of each master tuneable to meet the target performances of different applications.
SPEAR-09-H122 product overview 9/37 1.3 block diagram figure 2. block diagram spear head600 common subsystems basic subsystem dma (8-chan .) clcd controller rom (32kb ) flash serial configurable cell array subsystem low speed connect application subs . hs connect multi-layer bus interconnection matrix sdram controller ddr1-2 eth . gmac usb2.0 dev usb2.0 host usb2.0 host a b d cell array (applic. configurable) tmr tmr gpio spi adc c tmr wdg rtc gpio sys ctr misc uart uart spi spi i2c i/f control sram 32kb sram 32kb sram 32kb sram 32kb jpeg (codec ) flash nand ram (8kb ) irda cpu1 arm subsystem apb int ctr tmr gpio arm926ejs 16ki/16kd coproces. cache tcm -i/d i d
pin descriptio n SPEAR-09-H122 10/37 2 pin description 2.1 functional pin group with reference to figure package schematic in section 6 , here follows the pin list, sorted by their belonging ip. all supply and ground pins are classified as power signals and gathered in the ta b l e 3 . table 2. pin description by functional group group signal name ball direction function pin type adc ain_0 w11 input adc analog input channel analog buffer 2.5v tolerant ain_1 v11 ain_2 v12 ain_3 w12 ain_4 w13 ain_5 v13 ain_6 v14 ain_7 w14 adc_vrefn w15 adc negative voltage reference adc_vrefp v15 adc positive voltage reference debug test_0 e15 input test configuration ports. for functional mode they have to be set to zero. ttl input buffer, 3.3 v tolerant, pd test_1 d14 test_2 e14 test_3 e13 test_4 d13 test_5 d12 ntrst d17 input test reset input ttl schmitt trigger input buffer, 3.3 v tolerant, pu tdo e17 output test data output ttl output buffer, 3.3v capable,4 ma tck e16 input test clock ttl schmitt trigger input buffer, 3.3 v tolerant, pu tdi d16 input test data input tms d15 input test mode select pl pl_gpio_0 p4 i/o programmable logic i/o ttl bidir buffer, 3.3v capable, 4ma 3.3v tolerant, pu
SPEAR-09-H122 pin description 11/37 pl pl_gpio_1 n4 i/o programmable logic i/o ttl bidir buffer, 3.3v capable, 4ma 3.3v tolerant, pu pl_gpio_2 n5 pl_gpio_3 n6 pl_gpio_4 m5 pl_gpio_5 m4 pl_gpio_6 m3 pl_gpio_7 m2 pl_gpio_8 m1 pl_gpio_9 l1 pl_gpio_10 l2 pl_gpio_11 l3 pl_gpio_12 l4 pl_gpio_13 l5 pl_gpio_14 k6 pl_gpio_15 k5 pl_gpio_16 k4 pl_gpio_17 k3 pl_gpio_18 k2 pl_gpio_19 k1 pl_gpio_20 j1 pl_gpio_21 j2 pl_gpio_22 j3 pl_gpio_23 j4 pl_gpio_24 j5 pl_gpio_25 h5 pl_gpio_26 h4 pl_gpio_27 h3 pl_gpio_28 h2 pl_gpio_29 h1 pl_gpio_30 g1 pl_gpio_31 g2 pl_gpio_32 g3 pl_gpio_33 g4 pl_gpio_34 g5 pl_gpio_35 f5 table 2. pin description by functional group (continued) group signal name ball direction function pin type
pin descriptio n SPEAR-09-H122 12/37 pl pl_gpio_36 f4 i/o programmable logic i/o ttl bidir buffer, 3.3v capable, 4ma 3.3v tolerant, pu pl_gpio_37 f3 pl_gpio_38 f2 pl_gpio_39 f1 pl_gpio_40 e4 pl_gpio_41 e3 pl_gpio_42 e2 pl_gpio_43 e1 pl_gpio_44 d3 pl_gpio_45 d2 pl_gpio_46 d1 pl_gpio_47 c2 pl_gpio_48 c1 pl_gpio_49 b1 pl_gpio_50 a1 pl_gpio_51 b2 pl_gpio_52 a2 pl_gpio_53 c3 pl_gpio_54 b3 pl_gpio_55 a3 pl_gpio_56 b4 pl_gpio_57 c4 pl_gpio_58 d4 pl_gpio_59 e5 pl_gpio_60 d5 pl_gpio_61 c5 pl_gpio_62 b5 pl_gpio_63 b6 pl_gpio_64 c6 pl_gpio_65 d6 pl_gpio_66 e6 pl_gpio_67 f6 pl_gpio_68 f7 pl_gpio_69 e7 pl_gpio_70 d7 table 2. pin description by functional group (continued) group signal name ball direction function pin type
SPEAR-09-H122 pin description 13/37 pl pl_gpio_71 c7 i/o programmable logic i/o ttl output buffer 3.3v capable, 4ma ttl input buffer 3.3v tolerant, pu pl_gpio_72 b7 pl_gpio_73 e8 pl_gpio_74 d8 pl_gpio_75 c8 pl_gpio_76 b8 pl_gpio_77 a8 pl_gpio_78 c9 pl_gpio_79 d9 pl_gpio_80 e9 pl_gpio_81 e10 pl_gpio_82 d10 pl_gpio_83 c10 pl_clk_1 a7 programmable logic external clock ttl bidir buffer, 3.3v capable, 8ma 3.3v tolerant, pu pl_clk_2 a6 pl_clk_3 a5 pl_clk_4 a4 ethernet gmii_txclk f22 output transmit clock (gmii) ttl output buffer 3.3v capable, 8ma gmii_txclk125 e22 input ext. clock ttl input buffer, 3.3v tolerant, pd mii_txclk d22 transmit clock mii txd_0 f21 output transmit data ttl output buffer 3.3v capable, 8ma txd_1 e21 txd_2 f20 txd_3 e20 gmii_txd_4 d21 i/o ttl bidir buffer 3.3v capable, 8ma 3.3v tolerant, pd gmii_txd_5 d20 gmii_txd_6 c22 gmii_txd_7 c21 tx_er d18 output tr a n s m i t e r r o r ttl output buffer 3.3v capable, 8ma tx_en d19 transmit enable rx_er c20 input receive error ttl input buffer 3.3v tolerant, pd rx_dv c19 receive data valid rx_clk a22 receive clock rxd_0 b22 receive data table 2. pin description by functional group (continued) group signal name ball direction function pin type
pin descriptio n SPEAR-09-H122 14/37 ethernet rxd_1 b21 input receive data ttl input buffer 3.3v tolerant, pd rxd_2 a21 rxd_3 b20 gmii_rxd_4 a20 i/o ttl bidir buffer 3.3v capable, 8ma 3.3v tolerant, pd gmii_rxd_5 b19 gmii_rxd_6 a18 gmii_rxd_7 a19 col a17 input collision detect ttl input buffer 3.3v tolerant, pd crs b17 carrier sense mdio b18 i/o management data i/o ttl bidir buffer 3.3v capable, 4ma 3.3v tolerant, pd mdc c18 output management data clock ttl output buffer 3.3v capable, 8ma gpio gpio_0 w18 i/o general purpose i/o ttl bidir buffer 3.3v capable, 8ma 3.3v tolerant, pu gpio_1 v18 gpio_2 u18 gpio_3 t18 gpio_4 w19 gpio_5 v19 gpio_6 u19 gpio_7 t19 gpio_8 r19 gpio_9 r18 lcd i/f cld_0 y20 output lcd data ttl output buffer 3.3v capable, 8ma cld_1 y21 cld_2 y22 cld_3 w22 ttl output buffer 3.3v capable, 8ma cld_4 w21 cld_5 w20 cld_6 v20 cld_7 v21 cld_8 v22 cld_9 u22 cld_10 u21 table 2. pin description by functional group (continued) group signal name ball direction function pin type
SPEAR-09-H122 pin description 15/37 lcd i/f cld_11 u20 output lcd data ttl output buffer 3.3v capable, 8ma cld_12 t20 cld_13 t21 cld_14 r21 cld_15 r20 cld_16 p19 cld_17 p20 cld_18 p21 cld_19 n21 cld_20 n20 cld_21 n19 cld_22 m20 cld_23 m21 clac t22 stn ac bias drive tft data enable clcp r22 lcd panel clock clfp p22 stn frame pulse tft vertical sync cllp n22 stn line pulse tft horizontal sync clle m22 line end clpower m19 lcd power enable ddr i/f ddr_add_0 ab3 address line sstl_2/sstl_18 ddr_add_1 ab4 ddr_add_2 aa4 ddr_add_3 y4 ddr_add_4 w4 ddr_add_5 w5 ddr_add_6 y5 ddr_add_7 aa5 ddr_add_8 ab5 ddr_add_9 ab6 ddr_add_10 aa6 ddr_add_11 y6 ddr_add_12 w6 ddr_add_13 w7 table 2. pin description by functional group (continued) group signal name ball direction function pin type
pin descriptio n SPEAR-09-H122 16/37 ddr i/f ddr_add_14 y7 output address line sstl_2/sstl_18 ddr_ba_0 y9 bank select ddr_ba_1 w9 ddr_ba_2 w10 bank select ddr_ras ab7 row strobe ddr_cas aa7 column strobe ddr_we aa8 write enable ddr_clken ab8 clock enable ddr_clk_p aa9 differential clock differential sstl_2/sstl_18 ddr_clk_n ab9 ddr_cs_0 y8 chip select sstl_2/sstl_18 ddr_cs_1 w8 chip select sstl_2/sstl_18 ddr_odt_0 ab2 on-die termination enable lines ddr_odt_1 ab1 ddr_data_0 ab11 i/o data lines (lower byte) ddr_data_1 aa10 ddr_data_2 ab10 ddr_data_3 y10 ddr_data_4 y11 ddr_data_5 y12 ddr_data_6 ab12 ddr_data_7 aa12 ddr_dqs_0 ab13 differential lower data strobe differential sstl_2/sstl_18 ddr_ndqs_0 aa13 ddr_dm_0 aa11 output lower data mask sstl_2/sstl_18 ddr_gate_0 y13 i/o lower gate open ddr_data_8 ab15 data lines (upper byte) ddr_data_9 aa16 ddr_data_10 ab16 ddr_data_11 y16 ddr_data_12 y15 ddr_data_13 y14 ddr_data_14 ab14 table 2. pin description by functional group (continued) group signal name ball direction function pin type
SPEAR-09-H122 pin description 17/37 ddr i/f ddr_data_15 aa14 i/o data lines (upper byte) sstl_2/sstl_18 ddr_dqs_1 ab17 differential upper data strobe differential sstl_2/sstl_18 ddr_ndqs_1 aa17 ddr_dm_1 aa15 output upper data mask sstl_2/sstl_18 ddr_gate_1 y17 i/o upper gate open ddr_vref v10 input reference voltage analog ddr_comp_2v5 v9 output ext. resistor 2.5v analog ddr_comp_gnd v8 - common return for ext. resistors power ddr_comp_1v8 v7 output ext. resistor 1.8v analog ddr2_en d11 input configuration ttl input buffer 3.3v tolerant, pu usb dev_dp v1 i/o usb device d+ bidirectional analog buffer 5v tolerant dev_dm v2 usb device d- dev_vbus r4 input usb device vbus ttl input buffer 3.3v tolerant, pd host1_dp t1 i/o usb host1 d+ bidirectional analog buffer 5v tolerant host1_dm t2 usb host1 d- host1_vbus p5 output usb host1 vbus ttl output buffer 3.3v capable, 4ma host1_ovrc p6 input usb host1 over-current ttl input buffer 3.3v tolerant, pd host2_dp p1 i/o usb host2 d+ bidirectional analog buffer 5v tolerant host2_dm p2 usb host2 d- host2_vbus r5 output usb host2 vbus ttl output buffer 3.3v capable, 4ma host2_ovrc r6 input usb host2 over-current ttl input buffer 3.3v tolerant, pd usb_rref u4 output reference resistor analog master clock mclk_xi y1 input 30 mhz crystal i oscillator 2.5v capable mclk_xo y2 output 30 mhz crystal o rtc rtc_xi a9 input 32khz crystal i oscillator 1v capable rtc_xo b9 output 32 khz crystal o smi smi_datain l21 input serial flash input data ttl input buffer 3.3v tolerant, pu table 2. pin description by functional group (continued) group signal name ball direction function pin type
pin descriptio n SPEAR-09-H122 18/37 smi smi_dataout l20 output serial flash output data ttl output buffer 3.3v capable, 4ma smi_clk l22 serial flash clock smi_cs_0 l19 serial flash chip selects smi_cs_1 l18 spi ssp_1_mosi aa21 i/o master out slave in ttl bidir buffer 3.3v capable, 8ma 3.3v tolerant, pu ssp_1_miso ab21 i/o master in slave out ssp_1_sclk ab22 i/o serial clock ssp_1_ss aa22 i/o slave select ssp_2_mosi k20 i/o master out slave in ssp_2_miso k21 i/o master in slave out ssp_2_sclk k22 i/o serial clock ssp_2_ss_0 k19 i/o slave select ssp_2_ss_1 k18 i/o slave select ssp_3_mosi j20 i/o master out slave in ssp_3_miso j21 i/o master in slave out ssp_3_sclk j22 i/o serial clock ssp_3_ss j19 i/o slave select uart uart1_txd aa19 output serial data out ttl output buffer 3.3v capable, 4ma uart2_txd aa20 output uart1_rxd ab19 input serial data in ttl input buffer 3.3v tolerant, pd uart2_rxd ab20 input firda firda_txd aa18 output serial data out ttl output buffer 3.3v capable, 4ma firda_rxd ab18 input serial data in ttl input buffer 3.3v tolerant, pu i 2 c sda y18 i/o serial data in/out ttl bidir buffer 3.3v capable, 4ma 3.3v tolerant, pu scl y19 i/o serial clock nand flash i/f nf_io_0 h19 i/o data ttl bidir buffer 3.3v capable, 4ma 3.3v tolerant, pu table 2. pin description by functional group (continued) group signal name ball direction function pin type
SPEAR-09-H122 pin description 19/37 nand flash i/f nf_io_1 h18 i/o data ttl bidir buffer 3.3v capable, 4ma 3.3v tolerant, pu nf_io_2 g19 nf_io_3 g18 nf_io_4 f19 nf_io_5 f18 nf_io_6 e18 nf_io_7 e19 nf_ce g20 output chip enable ttl output buffer 3.3v capable, 4ma nf_re g22 read enable nf_we h20 write enable nf_ale h21 address latch enable nf_cle g21 command latch enable nf_wp j18 write protect nf_rb h22 input read/busy ttl input buffer 3.3v tolerant pu mreset c17 input main reset ttl schmitt trigger input buffer, 3.3 v tolerant, pu lv d s i/f ph0 a16 output general purpose i/o with lvds transceiver lvds driver ph0n b16 ph1 c16 ph1n c15 ph2 a15 ph2n b15 ph3 a14 ph3n b14 ph4 c14 ph4n c13 ph5 a13 ph5n b13 ph6 a12 ph6n b12 ph7 c12 ph7n c11 ph8 a11 input lvds receiver table 2. pin description by functional group (continued) group signal name ball direction function pin type
pin descriptio n SPEAR-09-H122 20/37 note: pu means pull up and pd means pull down lv d s i/f ph8n b11 input general purpose i/o with lvds transceiver lvds receiver digital_rext e11 output configuration analog 3.3v capable table 2. pin description by functional group (continued) group signal name ball direction function pin type table 3. power supply signal name ball value gnd j9, j10, j11, j12, j13, j14, k9 , k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, m9, m10, m11, m12, m13, m14, n9, n10, n11, n12, n13, n14, p9 , p10, p11, p12, p13, p14, m18, n18, p18, t5, v6, n2, r1, u2, t4, w3, w2, y3, aa3, v5, u5, v17, u17, a10, e12 0 v agnd v16 0 v v dd 3 j6, h6, f8, f9, f16, h17, k17, l17, n17, p17, m6, f17 3.3 v v dd g6, l6, g17, m17, r17, f10, f1 3, f15, j17, t6, u13, u10, u16 1.0 v host2_v dd bc n1 2.5 v host2_v dd bs n3 1.0 v host2_v dd b3 r3 3.3 v host1_v dd bc p3 2.5 v host1_v dd bs r2 1.0 v host1_v dd b3 r3 3.3 v device_v dd bc u1 2.5 v device_v dd bs u3 1.0 v device_v dd b3 t3 3.3 v usb_pll_v dd p v3 1.0 v usb_pll_v dd p2v5 w1 2.5 v mclk_v dd aa1 1.0 v mclk_v dd 2v5 aa2 2.5 v dith_v dd 2v5 v4 2.5 v dith_v dd u6 1.0 v sstl_v dd e u7, u8, u9, u11, u12, u14, u15 1.8/2.5 v adc_av dd w16 2.5 v ddr_pll_av dd w17 2.5 v ddr_pll_v dd t17 1.0 v lv d s _ v dd f11, f12, f14 2.5 v rtc_v dd b10 1.0 v
SPEAR-09-H122 pin description 21/37 2.2 special ios 2.2.1 usb 2.0 transceiver spear head600 has three usb 2.0 multimode atx transceivers. one transceiver will be used by the usb device controller, and tw o will be used by the hosts. these are all integrated into a sing le usb three-phy macro. 2.2.2 sstl_2/sstl_18 t. b . d. 2.2.3 lvds t. b . d.
memory map SPEAR-09-H122 22/37 3 memory map 3.1 main memory map 3.2 icm1 - low speed connection table 4. main memory map start address end address peripheral notes 0x0000.0000 0x3fff.ffff external sdram ddr1 or ddr2 0x4000.0000 0xbfff.ffff ras_n/m programmable logic array 0xc000.0000 0xcfff.f7ff ahb_eh2h exp. interface 0xcfff.f800 0xcfff.fff f ahb_eh2h registers 0xd000.0000 0xd7ff.ffff icm1 low speed connection 0xd800.0000 0xdfff.ffff ic m2 application subsystem 0xe000.0000 0xe7ff.ffff icm4 high speed connection 0xe800.0000 0xefff.ffff reserved 0xf000.0000 0xf7ff.ffff ml1,2 mul ti layer cpu subsystem 0xf800.0000 0xfff f.ffff icm3 basic subsystem table 5. icm1 - low speed connection start address end address peripheral notes bus 0xd000.0000 0xd007.ffff uart 1 apb 0xd008.0000 0xd00f.ffff uart 2 apb 0xd010.0000 0xd017.ffff spi 1 apb 0xd018.0000 0xd01f.ffff spi 2 apb 0xd020.0000 0xd027.ffff i2c apb 0xd028.0000 0xd07f.ffff - reserved - 0xd080.0000 0xd0ff. ffff jpeg codec ahb 0xd100.0000 0xd17f.ffff irda ahb 0xd180.0000 0xd1ff.ffff fsmc nand flash controller ahb 0xd200.0000 0xd27f.ffff fsmc nand flash memory ahb 0xd280.0000 0xd7ff.ffff sram stat ic ram shared memory (8kb) ahb
SPEAR-09-H122 memory map 23/37 3.3 icm2 - application subsystem 3.4 icm4 - high speed connection table 6. icm2 - application subsystem start address end address peripheral notes bus 0xd800.0000 0xd807.ffff timer 1 apb 0xd808.0000 0xd80f.ffff timer 2 apb 0xd810.0000 0xd817.ffff gpio apb 0xd818.0000 0xd81f.ffff spi 3 apb 0xd820.0000 0xd827.ffff adc apb 0xd828.0000 0xdfff.ffff - reserved table 7. icm4 - high speed connection start address end address peripheral notes bus 0xe000.0000 0xe07f.ffff - reserved apb 0xe080.0000 0xe0ff.ffff ethernet ctrl gmac ahb 0xe100.0000 0xe10f.ffff u sb2.0 device fifo ahb 0xe110.0000 0xe11f.ffff usb2.0 device configuration registers ahb 0xe120.0000 0xe12f.ffff usb2 .0 device plug detect ahb 0xe130.0000 0xe17f.ffff - reserved ahb 0xe180.0000 0xe18f.fff f usb2.0 ehci 1 ahb 0xe190.0000 0xe19f.ffff usb2.0 ohci 1 ahb 0xe1a0.0000 0xe1ff.ffff - reserved ahb 0xe200.0000 0xe20f.fff f usb2.0 ehci 2 ahb 0xe210.0000 0xe21f.ffff usb2.0 ohci 2 ahb 0xe220.0000 0xe2ff.ffff - reserved ahb 0xe280.0000 0xe280.ffff ml usb arb configuration register ahb 0xe290.0000 0xe7ff.ffff - reserved ahb
memory map SPEAR-09-H122 24/37 3.5 ml1, 2 - multi layer cpu subsystem 3.6 icm3 - basic subsystem table 8. ml1, 2 - multi layer cpu subsystem start address end address peripheral notes bus 0xf000.0000 0xf00f.ffff timer apb 0xf010.0000 0xf01f.ffff gpio apb 0xf020.0000 0xf0ff.ffff - reserved ahb 0xf100.0000 0xf10f.ffff itc secondary ahb 0xf110.0000 0xf11f.ffff itc primary ahb 0xf120.0000 0xf7ff.ffff - reserved ahb table 9. icm3 - basic subsystem start address end address peripheral notes 0xf800.0000 0xfbff.ffff serial flash memory 0xfc00.0000 0xfc1f.ffff serial flash controller 0xfc20.0000 0xfc3f.ffff lcd controller 0xfc40.0000 0xfc5f.ffff dma controller 0xfc60.0000 0xfc7f.ffff sdram controller 0xfc80.0000 0xfc87.ffff timer 0xfc88.0000 0xfc8f.ffff watch dog timer 0xfc90.0000 0xfc97.ffff real time clock 0xfc98.0000 0xfc9f.ffff general purpose i/o 0xfca0.0000 0xfca7.ffff system controller 0xfca8.0000 0xfcaf.ffff miscellaneous registers 0xfcb0.0000 0xfeff.ffff - reserved 0xff00.0000 0xffff.ffff internal rom boot
SPEAR-09-H122 main blocks 25/37 4 main blocks 4.1 7.1 cpu subsystem 4.1.1 overview the cpu sub-system includes the following blocks: arm 926ejs two timer channels one gpio block (8 i/o lines) two interrupt controller (32 irq lines) 4.1.2 cpu arm 926ej-s the processor is the powerful arm926ej-s, targeted for multi-tasking applications. belonging to arm9 general purposes family microprocessor, it principally stands out for the memory management unit, which provides virtually memory features, making it also compliant with windowsce, linux and symbianos operating systems. the arm926ej-s supports the 32 bit arm and 16 bit thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of java byte codes. besides, it has the arm debug architecture and includes logic to assist in software debug. its main features are: core f max 333 mhz independent programmable for each cpu memory management unit 16 kb of instruction cache 16 kb of data cache configurable t ightly c oupled m emory (i/d) size trough the configurable logic array arm-v5tej instructions set architecture: ? arm (32 bit), thumb ? (16 bit) ? dsp extensions ? java? (8 bit) instructions. amba bus interface coprocessor interface embeddedice-rt ? single mode (two connectors) ? two processor daisy chained etm9 (embedded trace macro-cell) ? single etm mode (single or double packet configurable) ? dual etm mode (both processors etm are available in single packet mode)
main blocks SPEAR-09-H122 26/37 4.2 clock and reset system the clock system block is a fully programmable block able to generate all clocks necessary at the chip. the clocks, at default operative frequency, are: clock @ 333 mhz for the cpus. (note 1) clock @ 166 mhz for ahb bus and ahb peripherals. (note 1) clock @ 83 mhz for, apb bus and apb peripherals. (note 1) clock @ 100-333 mhz for ddr memory interface. (note 2) the frequencies are the maximum allowed value and the user can modify them by programming dedicated registers. the clock system consists of 2 main parts: a multi-clock generator block and an two internal pll. the multi-clock generator block, starting from a reference signal (which generally is delivered from the pll), gene rates all clocks for the ips of spear head600 according to dedicated programmable registers. each pll, starting from the oscillator input of 30 mhz, g enerates a clock signal at a frequency corresponding at the highest of the group, which is the reference signal used by the multi-clock generator block to obtain all the other requested clocks for the group. its main features is the electro-magnetic inte rference reduction capa bility: user has the possibility to set up the pll in order to modulate with a triang ular wave to the vco clock; the resulting signal will have the spectrum (and the power) spread on a small range (programmable) of frequencies centered on f0 (vco freq.), obtaining minimum electromagnetic emissions. this method replace all the other traditional methods of e.m.i. reduction, as filtering, ferrite beads, chokes, adding power layers and ground planets to pcbs, metal shielding etc., allowing se nsible cost saving for customers. note: 1 this frequency is based on the pll1. 2 this frequency is based on the pll2. 4.3 main oscillator 4.3.1 crystal connection figure 3. crystal connection v dd 2 v 5 33 pf 30 mhz xi xo 33 pf
SPEAR-09-H122 main blocks 27/37 4.3.2 crystal equivalent model figure 4. crystal equivalent model 1. co is the parasitic capac itance of the crystal package 2. cl1 and cl2 are the capac itance on each resonator pad 4.4 rtc oscillator 4.4.1 rtc crystal connection figure 5. rtc crystal oscillator table 10. main oscillator characteristics supplier rm(ohms ) lm(mh) cm(ff) co(pf) q(k) epson (e31821) 9.3 5.9 4.8 1.7 120 raltron (m3000) 9.6 2.6 10.8 3.5 45 kss (kss3kf) 5 3.2 8.7 2.7 121 v dd 2 v 5 co cl 1 cl 2 cm rm lm xi xo gnd 27 pf 30 mhz xi xo 27 pf
main blocks SPEAR-09-H122 28/37 4.4.2 rtc crystal equivalent model figure 6. rtc crystal equivalent model 1. co is the parasitic capac itance of the crystal package 2. cl1 and cl2 are the capac itance on each resonator pad table 11. rtc oscillator characteristics supplier rm(kohms) lm(mh) cm(ff) co(pf) ecliptek <65 10 1.9 0.85 co cl 1 cl 2 cm rm lm xi xo gnd
SPEAR-09-H122 main blocks 29/37 4.5 ethernet controller compliant with the ieee 802.3-2002 standard. gmii or mii interface to the external phy. it supports 10/100/1000 mbps data transfer rates with any one or a combination of the phy interfaces above; local fifo available (4kbyte rx, 2kbyte tx). it supports both half-duplex and full-duplex operation. in half-duplex operation, csma/cd protocol is provided for, as well as packet bursting and frame extension at 1000 mbps. programmable frame length to support both standard and jumbo ethernet frames with size up to 16 kbytes. a variety of flexible addresses filtering modes are supported. a set of control and status registers (csrs) to control gmac core operation. native dma with single-channel transmit and receive engines, providing 32/64/128-bit data transfers. dma implements dual-buffer (ring) or linked-list (chained) descriptor chaining. an ahb slave acting as programming interface to access all csrs, for both dma and gmac core subsystems. an ahb master for data transfer to system memory. 32-bit ahb master bus width, supporting 32, 64, and 128-bit wide data transactions. 4.6 usb2 host controller spear head600 has two fully ind ependent usb 2.0 host s and each one is constituted with 5 major blocks: ehci able to manage the high speed transfer (hs - 480 mbits). ohci that manages the full and the low speed transfer (12 and 1.5 mbits). local fifo having size of 2 kbyte local dma integrated usb2 transceiver (phy). both the hosts are capable to manage an external power switch providing the control line to enable or disable the power and also having an input line to sense the over-current condition detected by the external switch.
main blocks SPEAR-09-H122 30/37 4.7 usb2 device controller it supports the 480 mbps high-speed (hs) for usb 2.0, as well as the 12 mbps full- speed (fs) and the low-speed (ls) for usb 1.1. it supports 16 physical endpoints and proper configurations to achieve logical endpoints. integrated usb transceiver (phy) local fifo having size of 4 kbyte shared among all the endpoints. both dma mode and slave-only mode supported. in dma mode, the udc supports descriptor-based memory structures in application memory. in both modes, an ahb slave is provided by udc-ahb, acting as programming interface to access to memory-mapped control and status registers (csrs); an ahb master for data transfer to system memory is provided, supporting 8, 16, and 32-bit wide data transactions on the ahb bus. a usb plug detect (upd) which detects the connection of a cable. 4.8 low jitter pll within the usb hosts and device a local low jitter pll is provided to meet the usb2.0 specification requirements. ep0 control (in/out) ep1~15 software configurable to: ?bulk in ?bulk out ? interrupt in ? interrupt out ? isochronous.
SPEAR-09-H122 main blocks 31/37 4.9 reconfigurable logic array 4.9.1 overview the configurable logic array consists of an embedded macro where it is possible to implement a custom project by mapping up to 600k equivalent gates. this macro is interfaced wit h the rest of the system by some ahb bus, some memory channels and has a direct connection to the 1s t arm processor internal bus. in this way is also possible to customize the tcm memory or add a coprocessor using this macro. the following memory cuts are available to this block: 4 cuts single port with size of 8kb each 8 cuts single port with size of 4kb each 16 cuts single port with size of 2kb each 8 cuts dual port with size of 2kb each 4 cuts dual port with size of 4kb each the array is also connected to 88 i/o (3.3v ca pable/tolerant and 4 ma sink/source) plus 9 lvds lines (one input and 8 outputs). the following clocks can be used in the integrated logic: 5 different coming from the external balls 4 different coming from the integrated frequency synthesizer pll1 frequency pll2 frequency 48 mhz (usb pll) 30 mhz (main oscillator) 32.768 khz (rtc oscillator) apb clock (programmable) ahb clock (programmable) 4.9.2 custom project development the flow to develop a custom project to em bed in the spear head60 0 is similar to the standard asic flow. the configurable logic is an empty module of the whole system on chip. pin out and maximum gates are fixed. the hdl project is synthesized using dedicated library and post synthesis simulation is possible to verify the custom net-list. regarding the back end flow, after the place and route phase the verification procedure is the same as a standard asic flow. 4.9.3 customization process the layers used for the ip configuration range fr om 2 metals - 1 via up to 4 metals - 4 vias. diffusion and remaining metal/vias are invari ant across multiple cu stom designs. density and performance scale with number of customization layers. the configurable logic includ ed in the spear head600 chip is a 600kgates equivalent array when customized using 4 metals - 4 vias.
main blocks SPEAR-09-H122 32/37 4.9.4 adc controller successive approximation adc; 10 bit resolution; up to 1 msps; analog input (ain) channels, ranging from 0 to 2.5 v; inl 1 lsb, dnl 1 lsb; programmable conversion speed, (min conversion time is 1 s). programmable average results from 1 (no average) up to 128. 4.10 other interfaces 4.10.1 uart two uart are provided with the following features: separate 16x8 (16 location deep x 8-bit wide) transmit and 16x12 receive fifos to reduce cpu interrupts; speed up to 560.8 kbps. 4.10.2 spi three spi are provided. the main features are: max speed of 40 mbps programmable choice of interface operation spi, microwire or ti synchronous serial programmable data frame size from 4 to 16 bit. the spi controllers can deal with master and slave mode. a connection with general purpose dma is provided to reduce the cpu load.
SPEAR-09-H122 electrical characteristics 33/37 5 electrical characteristics 5.1 absolute maximum ratings this product contains devices to protect the inputs against damage due to high static voltages; however it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. the average chip-junction temperature, tj, can be calculated using the following equation: t j = t a + (p d j a ) where: t a is the ambient temperature in c j a is the package junction-to-ambient thermal resistance, which is 34 c/w p d = p int + p port ?p int is the chip internal power ?p port is the power dissipation on input and output pins; user determined if p port is neglected, an approximate relationship between pd is: p d = k / (t j + 273 c) and, solving first equations: k = p d (t a + 273 c) + j a x p d 2 k is a constant for the particular, which can be determined through last equation by measuring p d at equilibrium, for a know t a using this value of k, the value of p d and t j can be obtained by solving first and second equation, iteratively for any value of t a . table 12. absolute maximum ratings symbol parameter value unit v dd core supply voltage core 1.6 v v dd i/o supply voltage i/o 4.8 v v dd pll supply voltage pll v v dd ddr1 supply voltage dram i/f (ddr1) 4.8 v v dd ddr2 supply voltage dram i/f (ddr2) 4.8 v v dd rtc supply voltage rtc 1.6 v t j junction temperature -40 ~ 125 c t stg storage temperature -55 ~ 150 c
electrical characte ristics SPEAR-09-H122 34/37 5.2 dc electrical characteristics supply voltage specifications the recommended operating conditions are listed in the following table: table 13. dc electrical characteristics symbol parameter min. typ. max. unit v dd core supply voltage core 0.95 1 1.05 v v dd i/o supply voltage i/o 3 3.3 3.6 v v dd pll supply voltage pll 2.25 2.5 2.75 v v dd osc supply voltage oscillator 2.25 2.5 2.75 v v dd ddr1 supply voltage dram i/f (ddr1) 2.25 2.5 2.75 v v dd ddr2 supply voltage dram i/f (ddr2) 1.7 1.8 1.9 v v dd rtc supply voltage rtc 0.95 1 1.05 v t op operating temperature -40 85 c
SPEAR-09-H122 packa ge information 35/37 6 package information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 7. pbga420 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.81 0.0713 a1 0.27 0.0106 a2 1.305 0.0514 a3 0.52 0.0205 a4 0.785 0.0309 b 0.45 0.50 0.55 0.0177 0.0197 0.0217 d 22.80 23.00 23.20 0.8976 0.9055 0.9134 d1 21.00 0.8268 e 22.80 23.00 23.20 0.8976 0.9055 0.9134 e1 21.00 0.8268 e 1.00 0.0394 f 1.00 0.0394 ddd 0.20 0.0079 eee 0.25 0.0098 fff 0.10 0.0039 pbga420 (23x23x1.81mm) b all g rid a rray p ackage 7859856 a
revision history SPEAR-09-H122 36/37 7 revision history table 14. document revision history date revision changes 28-feb-2007 1 initial release.
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